If you are interested in post-graduate level studies / research in Device and Circuit Modeling (leading to Master or PhD degree) in Universiti Teknologi Malaysia,
please email me at firstname.lastname@example.org with your resume/CV. Applications must be made directly to the university.
For Malaysian applicant, there are many sources of funding available to you for studying in UTM.
Further details please click to these links:
MyBrain15: https://www.mohe.gov.my/MyBrain15UTM: http://www.sps.utm.my/sps/scholarship
PhD Research in Cambridge (2007 to 2011)
My PhD research is on the development of carbon nanotube field-effect transistor (CNTFET) and graphene nanoribbon field-effect transistor (GNRFET) device and circuit level models which can be transferred into standard electronic computer-aided design (ECAD) tools to enable digital logic circuit design. The simulation is based on semiconducting (20,0) zigzag CNT and (19,0) armchair GNR. The robust and comprehensive device, circuit and layout-based models are simulated in MATLAB, Synopsys HSPICE, Orcad PSPICE and Cadence custom IC tools. These are the objectives of the research
(i) To formulate analytical and semi-empirical equations for CNTFETs and GNRFETs
(ii) To implement circuit compatible compact device models for SPICE
(iii) To customize the physical layout of carbon channel MOSFET circuits compatible with 45 nm and 90 nm Si technology nodes
(iv) To explore the device and circuit performance based on physical and electrical parametric variations
(v) To investigate the circuit performance of CNTFETs and GNRFETs in prototype digital logic gates
(vi) To verify the accuracy the compact models with published experimental results and other accomplished models
M.Eng Research in UTM and Intel (2005 to 2006)
For my Master research, a newly developed short channel models is utilized to study velocity saturation in 90 nm silicon metal-oxide-semiconductor field-effect-transistor (MOSFET). The following are the objectives of the research
(i) To understand high field effects in nanoscale transistor in 90nm process technology.
(ii) To formulate simple analytical and semi-empirical equations for device model applicable to nanoscale devices by taking into account velocity saturation
(iii) To analyze velocity saturation effects on temperature, doping concentration, longitudinal and transverse electric field.